『The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations』のカバーアート

The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations

The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations

著者： Fexingo
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Lucas and Luna sit down at a lab bench cluttered with oscilloscopes and prototype boards to talk about the engineering decisions that shape the chips powering modern life. Each episode takes one piece of hardware — a new RISC-V core, a GaN power amplifier, a MEMS accelerometer — and examines its design trade-offs, yield challenges, and market positioning. They discuss why Intel’s 20A node matters for foundry customers, how TSMC’s CoWoS packaging affects AI accelerator supply, and what the CHIPS Act subsidies mean for domestic fab construction. Lucas brings the component-level knowledge (threshold voltages, die sizes, lithography steps); Luna pushes on the system-level implications (thermal constraints, software compatibility, supply chain risk). The listener is someone who reads datasheets for fun, follows EDA tool announcements, or needs to decide between an FPGA and an ASIC for their next product. No hot takes on Apple’s latest chip — just a careful look at what the die shot reveals and whether the architecture will trickle down to mid-range devices. Can a country really onshore advanced semiconductor manufacturing in a decade? How do you test a chip with billions of transistors? And what does the shift to chiplets mean for the engineer designing a PCB today? #SemiconductorIndustry #ChipDesign #HardwareEngineering #Electronics #TSMC #Intel #RISCV #GaN #MEMS #EDA #ASIC #FPGA #CHIPSAct #DieShot #EngineeringConversations #Technology #FexingoBusiness #BusinessPodcast Keep every episode free: buymeacoffee.com/fexingo© 2026 Fexingo. All rights reserved. 経済学
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  • How EUV Lithography Machines Make the Smallest Chips Possible

    How EUV Lithography Machines Make the Smallest Chips Possible
    2026/06/08
    In this episode of The Hardware Podcast, Lucas and Luna dive into the engineering marvel behind extreme ultraviolet lithography—the machines that print the world's tiniest transistors. They explain why EUV light is generated by vaporizing tiny droplets of tin with a laser, how mirrors replace lenses because UV light can't travel through glass, and the staggering precision required to align layers within a single nanometer. Lucas breaks down the monopoly of ASML, the Dutch company that builds every EUV system, and why each machine costs over $150 million. Luna brings a practical example: how a modern smartphone chip's 3-nanometer process relies on 30 to 80 EUV layers, each requiring a vacuum chamber the size of a bus. They discuss the physics of reflective optics, the challenge of plasma stability, and why this technology is the bottleneck for Moore's Law. A must-listen for anyone curious about the physical limits of computing. #EUV #Lithography #ASML #ChipManufacturing #Nanometer #Photonics #PlasmaPhysics #Semiconductor #MooreLaw #Transistor #Technology #Hardware #Engineering #FexingoBusiness #BusinessPodcast #TechPodcast #DeepTech #PhotonLithography Keep every episode free: buymeacoffee.com/fexingo
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    11 分
  • Why Chip Designers Are Betting on Chiplets

    Why Chip Designers Are Betting on Chiplets
    2026/06/07
    Episode 37 of The Hardware Podcast dives into the chiplet revolution — why major chipmakers are moving away from monolithic dies and stitching together smaller silicon tiles instead. Lucas explains how AMD's Zen architecture proved the model with its Zen 2 chiplet design, using four compute dies plus an I/O die on a single package. Luna questions the cost and complexity trade-offs, from interconnect standards like Universal Chiplet Interconnect Express (UCIe) to yield improvements and thermal challenges. They discuss how Intel, AMD, and emerging startups are adopting chiplets for everything from data center CPUs to AI accelerators, and what this shift means for the future of Moore's Law. A concrete look at why splitting chips apart is the smartest way to keep making them faster. #Chiplets #Semiconductor #AMD #ZenArchitecture #ChipDesign #AdvancedPackaging #UCIe #Moore'sLaw #Technology #Hardware #DataCenter #AI #CPU #Yield #Interconnect #FexingoBusiness #BusinessPodcast #TheHardwarePodcast Keep every episode free: buymeacoffee.com/fexingo
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    11 分
  • Why Chip Designers Are Betting on Advanced Packaging

    Why Chip Designers Are Betting on Advanced Packaging
    2026/06/07
    In Episode 36 of The Hardware Podcast, Lucas and Luna explore the quiet revolution in chip packaging that is extending Moore's Law. They explain how 2.5D and 3D packaging allow designers to combine chiplets from different process nodes, boosting performance without shrinking transistors. The hosts walk through a real example: how an AI accelerator uses interposers and hybrid bonding to stack memory directly on logic, slashing latency. They also touch on the role of TSMC's CoWoS and Intel's EMIB technologies, and why thermal management remains the biggest hurdle. Listeners will learn why packaging, not lithography, is now the frontier of chip innovation. #AdvancedPackaging #ChipDesign #Semiconductor #Moore'sLaw #Chiplets #2.5D #3DStacking #Interposer #HybridBonding #TSMC #CoWoS #Intel #EMIB #AIAccelerator #ThermalManagement #Technology #FexingoBusiness #BusinessPodcast Keep every episode free: buymeacoffee.com/fexingo
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    10 分
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