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  • How EUV Lithography Machines Make the Smallest Chips Possible

    How EUV Lithography Machines Make the Smallest Chips Possible
    2026/06/08
    In this episode of The Hardware Podcast, Lucas and Luna dive into the engineering marvel behind extreme ultraviolet lithography—the machines that print the world's tiniest transistors. They explain why EUV light is generated by vaporizing tiny droplets of tin with a laser, how mirrors replace lenses because UV light can't travel through glass, and the staggering precision required to align layers within a single nanometer. Lucas breaks down the monopoly of ASML, the Dutch company that builds every EUV system, and why each machine costs over $150 million. Luna brings a practical example: how a modern smartphone chip's 3-nanometer process relies on 30 to 80 EUV layers, each requiring a vacuum chamber the size of a bus. They discuss the physics of reflective optics, the challenge of plasma stability, and why this technology is the bottleneck for Moore's Law. A must-listen for anyone curious about the physical limits of computing. #EUV #Lithography #ASML #ChipManufacturing #Nanometer #Photonics #PlasmaPhysics #Semiconductor #MooreLaw #Transistor #Technology #Hardware #Engineering #FexingoBusiness #BusinessPodcast #TechPodcast #DeepTech #PhotonLithography Keep every episode free: buymeacoffee.com/fexingo
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    11 分
  • Why Chip Designers Are Betting on Chiplets

    Why Chip Designers Are Betting on Chiplets
    2026/06/07
    Episode 37 of The Hardware Podcast dives into the chiplet revolution — why major chipmakers are moving away from monolithic dies and stitching together smaller silicon tiles instead. Lucas explains how AMD's Zen architecture proved the model with its Zen 2 chiplet design, using four compute dies plus an I/O die on a single package. Luna questions the cost and complexity trade-offs, from interconnect standards like Universal Chiplet Interconnect Express (UCIe) to yield improvements and thermal challenges. They discuss how Intel, AMD, and emerging startups are adopting chiplets for everything from data center CPUs to AI accelerators, and what this shift means for the future of Moore's Law. A concrete look at why splitting chips apart is the smartest way to keep making them faster. #Chiplets #Semiconductor #AMD #ZenArchitecture #ChipDesign #AdvancedPackaging #UCIe #Moore'sLaw #Technology #Hardware #DataCenter #AI #CPU #Yield #Interconnect #FexingoBusiness #BusinessPodcast #TheHardwarePodcast Keep every episode free: buymeacoffee.com/fexingo
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    11 分
  • Why Chip Designers Are Betting on Advanced Packaging

    Why Chip Designers Are Betting on Advanced Packaging
    2026/06/07
    In Episode 36 of The Hardware Podcast, Lucas and Luna explore the quiet revolution in chip packaging that is extending Moore's Law. They explain how 2.5D and 3D packaging allow designers to combine chiplets from different process nodes, boosting performance without shrinking transistors. The hosts walk through a real example: how an AI accelerator uses interposers and hybrid bonding to stack memory directly on logic, slashing latency. They also touch on the role of TSMC's CoWoS and Intel's EMIB technologies, and why thermal management remains the biggest hurdle. Listeners will learn why packaging, not lithography, is now the frontier of chip innovation. #AdvancedPackaging #ChipDesign #Semiconductor #Moore'sLaw #Chiplets #2.5D #3DStacking #Interposer #HybridBonding #TSMC #CoWoS #Intel #EMIB #AIAccelerator #ThermalManagement #Technology #FexingoBusiness #BusinessPodcast Keep every episode free: buymeacoffee.com/fexingo
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    10 分
  • Why Chip Teams Are Rethinking On-Chip Memory

    Why Chip Teams Are Rethinking On-Chip Memory
    2026/06/06
    Episode 35 of The Hardware Podcast with Fexingo dives into the quiet revolution happening inside chip design: the shift away from traditional SRAM toward new on-chip memory architectures like embedded DRAM and resistive RAM. Lucas and Luna explain why memory now consumes 40 to 60 percent of chip area in a typical processor, and why the old cache hierarchy is breaking down. They explore a concrete example—Apple's M-series Ultra chips, which use a massive 192 MB of on-chip memory—and walk through the tradeoffs between density, latency, and power. The conversation also covers the challenges of integrating new memory materials into standard CMOS processes, and why companies like Intel and TSMC are betting on different approaches. If you've ever wondered why chip performance gains have slowed even as transistor counts keep rising, this episode offers a clear, ground-level explanation. #OnChipMemory #SRAM #EmbeddedDRAM #ResistiveRAM #RRAM #AppleSilicon #M3Ultra #Intel #TSMC #ChipDesign #MemoryWall #CacheHierarchy #Technology #Semiconductors #Hardware #HardwareEngineering #FexingoBusiness #BusinessPodcast Keep every episode free: buymeacoffee.com/fexingo
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    13 分
  • The Hidden Economics Behind Chip Packaging

    The Hidden Economics Behind Chip Packaging
    2026/06/06
    In Episode 34, Lucas and Luna unpack a quiet revolution that rarely makes headlines: advanced chip packaging. While everyone obsesses over transistor shrinks, the way chips get physically assembled is becoming a bottleneck and an opportunity. Lucas explains why TSMC's CoWoS packaging is suddenly critical for AI accelerators, how Intel is betting on Foveros, and why the cost per extra millimeter of silicon interposer can run into millions. Luna asks whether the packaging renaissance means old fabs can stay relevant. They also explore how substrate shortages—yes, the board underneath—are delaying high-end chips for months. Specific examples: NVIDIA's H100 supply constraints, Apple's UltraFusion packaging for M-series, and the $3 billion Samsung is investing in panel-level packaging. A clear look at the layer of hardware engineering most people overlook. #ChipPackaging #AdvancedPackaging #TSMC #CoWoS #IntelFoveros #SamsungPackaging #NVIDIAH100 #AppleUltraFusion #Semiconductor #ChipManufacturing #SubstrateShortage #AIHardware #HardwareEngineering #Technology #FexingoBusiness #BusinessPodcast #TheHardwarePodcast #ElectronicsEngineering Keep every episode free: buymeacoffee.com/fexingo
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    8 分
  • The Thermal Interface Material Keeping Your Chip Cool

    The Thermal Interface Material Keeping Your Chip Cool
    2026/06/05
    Every chip generates heat, but the material that moves that heat from the silicon to the heatsink rarely gets attention. In this episode, Lucas and Luna dive into thermal interface materials — the paste, pads, and liquid metals that sit between your CPU and its cooler. They break down how thermal conductivity is measured in watts per meter-kelvin, why a 1-micron air gap can kill performance, and what happens when a chip's thermal interface fails. Using the example of a 2024 consumer desktop processor that hit 95 degrees Celsius under load, they explain why TIM selection matters for both a phone's thin profile and a data center's power bill. No marketing fluff — just the physics of keeping silicon alive. #ThermalInterfaceMaterial #ChipCooling #ThermalConductivity #Semiconductor #HeatDissipation #CPU #ThermalPaste #LiquidMetal #ElectronicsEngineering #HardwareDesign #DataCenterCooling #SiliconPhysics #Technology #Engineering #FexingoBusiness #BusinessPodcast #Chips #Devices Keep every episode free: buymeacoffee.com/fexingo
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    12 分
  • The One Decision That Determines Every Chip Architecture

    The One Decision That Determines Every Chip Architecture
    2026/06/05
    Every chip design starts with a single high-stakes choice: which instruction set architecture to build on. This episode of The Hardware Podcast with Fexingo walks through why that decision shapes everything from performance to software ecosystem, with a close look at ARM's rise against x86 in data centers and how RISC-V is shaking up the landscape. Lucas and Luna break down the trade-offs between fixed ISA and custom extensions, the role of backward compatibility, and why Apple's M-series chips were a pivotal moment for ARM. They also explore the hidden costs of switching architectures and why startups are betting on RISC-V for specialized workloads. If you're curious about what gives a chip its DNA, this one's for you. #InstructionSetArchitecture #ARMvsx86 #RISCV #ChipDesign #AppleSilicon #DataCenterChips #HardwareEngineering #Technology #FexingoBusiness #BusinessPodcast #TechPodcast #Semiconductors #CPUArchitecture #SoftwareEcosystem #BackwardCompatibility #CustomExtensions #M1Chip #AmpereComputing Keep every episode free: buymeacoffee.com/fexingo
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    11 分
  • What Happens When Chip Interconnects Hit a Wall

    What Happens When Chip Interconnects Hit a Wall
    2026/06/04
    Lucas and Luna dig into the quiet crisis brewing inside every advanced chip: the interconnect bottleneck. As transistors shrink toward the atomic scale, the tiny wires that carry data between them are becoming the dominant limiter on performance and power. They break down why copper is struggling, what materials like cobalt and ruthenium might replace it, and how a shift to 'backside power delivery' is reshaping the entire chip stack. Specific numbers include the RC delay equation, resistance scaling laws, and why Intel's PowerVia technology matters. A concrete look at a problem most chip discussions skip. #ChipInterconnect #Semiconductor #CopperWiring #BacksidePowerDelivery #IntelPowerVia #Cobalt #Ruthenium #RCdelay #TSMC #Samsung #ChipDesign #Engineering #Technology #FexingoBusiness #BusinessPodcast #HardwarePodcast #ChipsDevices #ElectronicsEngineering Keep every episode free: buymeacoffee.com/fexingo
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    11 分